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As the feature size of NAND flash memory decreases, the threshold voltage signal becomes less reliable, and its distribution varies significantly with the number of program-erase (PE) cycles and the data retention time. We have developed parameter estimation algorithms to find the means and variances of the threshold voltage distribution that is modeled as a Gaussian mixture. The proposed methods...
Multi-level NAND flash memories with a 20nm design rule have been successfully developed for the first time. A 20nm rule wordline (WL) and bitline (BL) direction have been realized by Spacer Patterning Technology (SPT) of ArF immersion lithography. Key integration technologies include WL airgap with separate gate etch process and optimized control gate (CG) poly deposition process. In addition, many...
Recently solid state drive (SSD) based on NAND flash memory chips becomes popular in the consumer electronics market because it is tough on shock and its I/O performance is better than that of conventional hard disk drive. However, as the density of the semiconductor grows higher, the distance between its wires narrows down, their interferences are frequently occurred, and the bit error rate of semiconductor...
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