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This paper proposes a SAT-based formulation to evaluate the logical capacity of VIA-configurable block templates. The proposed solution is able to support any user-defined regular layout. The proposed SAT formulation was sucessufully applied to the three main VCSA fabrics in the literature considering transistor networks from an open cell library and transistor networks representing all 4-input Boolean...
This paper presents a novel yield model for integrated circuits manufacturing, considering lithography printability problems as a source of yield loss. The use of regular layouts can improve the printability of IC layouts, but it results in a significant area overhead by introducing regularity. To the best of our knowledge, this is the first approach that considers the tradeoff of cells with different...
Regular fabrics are expected to mitigate manufacturing process variations, increasing fabrication yield in deep sub-micron CMOS technologies. This paper presents an extensive analysis of aspects involved in the optimization of regular fabric (based) designs. The choice of the most efficient regular fabric design strategy depends on the area overhead and circuit performance degradation, which may vary...
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