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Reconfigurable Computing has been evolving as a new platform for satisfying the simultaneous demand for application performance and flexibility placed over the present day DSP market. Since signal processing algorithms place significant demand on the processing power of the underlying platform, high performance reconfigurable architectures promise to be very efficient. The performance of traditional...
This paper presents an analog to digital converter (ADC) capable of resolving 8 bits at a sampling rate of 250 MSPS. Primary objective of the design has been to make a trade-off between power consumption and resolution while keeping the sampling rate high. The parallel-pipeline architecture was best fit for such requirements. A new sub-ADC scheme has been introduced here to remove possible switch...
A novel current mode control scheme for the tristate boost converter circuit is proposed, which eliminates the zero in the right-half plane (RHP), and improves the dynamic performance. The tristate boost converter contains an additional switch across the inductor. Within a clock cycle, the inductor current first rises during the on interval of the main switch, then falls during the off or capacitor...
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