The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper reports new accurate and scalable behavioral modeling for novel 3D field-programmable ESD protection circuits using Verilog-A, which enables post-Si on-chip and insystem ESD protection design simulation and verification. New field-programmable ESD protection devices were fabricated in CMOS-compatible processes utilizing SONOS and nano crystal dots structures. The ESD behavior models were...
A new combined AC/DC-coupled output averaging technique for input amplifier design of flash analog-to-digital converters (ADC) is presented. The new offset averaging design technique takes full advantages of traditional DC-coupled resistance averaging and AC-coupled capacitance averaging techniques to minimize offset-induced ADC nonlinearities. Circuit analysis allows selection of optimum resistance...
This paper presents the optimization and design of a low-loss fixed-tuned 215-235-GHz sub-harmonic mixer, pumped by planar GaAs Schottky diodes fabricated by European company for space-borne radiometers. The circuits are fully integrated with the RF/IF filter and flip-chipped onto a suspended quartz-based substrate. The GaAs Gunn oscillator is used as the local-oscillator (LO) and this paper also...
This paper reviews key factors to practical ESD protection design for RF and analog/mixed-signal (AMS) ICs, including general challenges emerging, ESD-RFIC interactions, RF ESD design optimization and prediction, RF ESD design characterization, ESD-RFIC co-design technique, etc. Practical design examples are discussed. It means to provide a systematic and practical design flow for whole-chip ESD protection...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.