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The diminishing returns provided by voltage scaling have led to a recent paradigm shift toward so-called “approximate computing,” where computation accuracy is traded off for cost in error-tolerant applications. In this paper, a novel approach to achieving the power–performance–area versus data integrity tradeoff is proposed by integrating robust static memory cells and error-prone dynamic cells within...
An analog readout circuit for use in conjunction with the Planar-Hall-Effect Magnetic-Random-Access-Memory is presented. The non-volatile nature of this type of memory allows zero leakage during memory retention, allowing significant power saving. The circuit employs a novel technique for readout operation of memory bit-cells. The circuit uses chopping and switched-capacitor techniques for amplification...
Biomedical systems often require several kb of embedded memory and are typically operated in the subthreshold (sub-VT) domain for good energy-efficiency. Embedded memories and their leakage current can easily dominate the overall silicon area and the total power consumption, respectively. Gain-cell based embedded DRAM arrays provide a high-density, low-leakage alternative to SRAM for such systems;...
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