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In recent years, programmable interconnects in field programmable gate arrays (FPGAs) become a bottleneck of improving performance. So, for improving performance of FPGAs, a design of programmable interconnects is a key element, and innovative routing architecture is being desired. From this viewpoint, three dimensional FPGAs (3D-FPGAs) were proposed and focused. 3D-FPGAs have multiple layers which...
Two-rail logic circuits can be efficiently tested by non-codeword vector pairs. However, non-codeword vector pairs may sensitize some path delay faults which affect neither normal operation nor strongly fault secure property of the two-rail logic circuits. It means that testing with non-codeword vector pairs may be over-testing. This paper presents a construction of robust path delay fault test sets...
In the recent high-density and low-power VLSIs, occurrence of soft errors becomes significant problems. Recently, soft errors frequently occur on not only memory system but also circuits. Based on this standpoint, constructions of soft error tolerant FFs have been proposed. The FFs consist of some master and slave latches and C-elements. In the FFs, soft error pulses occurring on combinational parts...
In recent high-density, high-speed and low-power VLSIs, soft errors (SEs) and delay faults (DFs) frequently occur. Therefore, SE hardened design and DF testing are essential. This paper proposes three types of scan flip-flops (FFs) which have SE tolerant capability and allow enhanced scan shifting for DF testing, i.e. arbitrary two-pattern testing. The slave latches used in these FFs are constructed...
This paper proposes a BIST (built-in self test) method for testing the PEs (processing elements) of multi-context based dynamically reconfigurable processor. We use flip-flops existing in PEs to constitute the test circuit which has the function of LFSR (linear feedback shift register) and MISR (multiple input signature register) as DFT (design for testability). This method can reduce test execution...
Topics related to the faults in SRAM-based field programmable gate arrays (FPGAs) have been intensively studied in recent research studies. These topics include FPGA fault detection, FPGA fault diagnosis, FPGA defect tolerance, and FPGA fault tolerance. This paper provides a guided tour to the approaches related to these topics. These include techniques, which are applied to the FPGA and others which...
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