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This paper presents a solution to handling complex multi-group symmetry constraints in the placement design using transitive closure graph (TCG) representation for analog layouts. We propose a set of symmetric-feasible conditions, which can automatically satisfy symmetry requirements. We also develop a new contour-based packing scheme with time complexity of O(g??n??lgn), where g is the number of...
This paper presents a solution to handling multiple symmetry constraints in the placement design using transitive closure graph (TCG) representation for analog layouts. We propose a set of symmetric-feasible conditions, which can guarantee symmetric placement of sensitive cells with respect to multiple symmetry axes for reduction of parasitic mismatch and thermal gradients. We also develop a new contour-based...
Bulk-driven MOSFET technique meets the low-voltage and low-power requirements demanded in the modern analog circuit design. Due to submicron/nanometer technologies and critical short-channel effects, choosing a suitable MOSFET model for circuit design becomes increasingly important. However, the conventional MOSFET models normally set up for the typical gate-driven applications may not perform correctly...
Performance of analog circuits is highly sensitive to layout parasitics. This paper presents an improved algorithm that automatically conducts performance-constrained parasitic-aware retargeting and optimization of analog layouts. In order to meet the desired circuit specification, performance sensitivities with respect to layout parasitics are first determined. Then the algorithm applies sensitivity-based...
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