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An improved negative level shifter with high speed and low power consumption is presented. To reduce the switching delay and power consumption, a boost circuit is designed and additional charging current paths are introduced in the improved level shifter. The circuit has been designed in 130nm triple-well standard CMOS technology with a nominal power supply VDD of 1.5V and a negative voltage of -4...
In this paper, the novel mechanical switch device: suspended-gate FET is applied to FPGA development. This device offers almost an ideal subthreshold swing and a hysteretic resistance switching, opening opportunities for low-power applications. The proposed device can be used as the building block of programmable elements and memory of an FPGA. Based on this device, the proposed FPGA architecture,...
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