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This paper investigates sub-synchronous resonance (SSR) phenomena inside a doubly-fed induction generator (DFIG) based wind farm, considering the impact of the spatial distribution of wind speed. Firstly, the impedance model of a one-DFIG aggregated model based wind farm is presented to analyze the induction generator effect. Then, a two-DFIGs aggregated impedance model, considering DFIGs in both...
A two-stage drain current phenomenon in saturation region, named as Id-Vd hump, has been investigated in high-voltage NMOS transistor. A parasitic BJT turn-on enhanced Id-Vd hump model is proposed and characterized by using a two-dimensional device simulation. By optimizing channel/drift-region process conditions, both parasitic BJT and impact-ionization generation can be suppressed. Both measured...
A new CuxSiyO resistive memory, which is different from Cu-doped SiO2 or CuxO binary oxide, is integrated successfully in standard logic technology for the first time. Key breakthrough is that data retention (10 years@ 150°C), resistance distribution (with 50x window@125°C ) and disturbance immunity significantly improved with integration simplicity advantage, as demonstrated on a 1Mb test chip. The...
A CuxO-based resistive memory is successfully integrated in 0.13 μm logic process. Operation algorithm is optimized to achieve low power consumption with reset current down to 30 μA. High thermal stability and small cell size less than 22 F2 have been demonstrated. The advantages make this device promising for system on chip non-volatile memory applications.
The root causes of the high voltage (HV) LDMOS (Fig. 2) failed at the low voltage electrostatic-discharge (ESD) zap is found. One is caused by the bulk layout and one is caused by the intrinsic characteristic of the device. From the findings, a new structure is proposed to eliminate the root causes without sacrificing the IV characteristics and dimension of the device.
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