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The randomness of photovoltaic power generation and reactive load will impact on the operation of distribution network. To improve this situation, reactive power compensation technology of DSTATCOM is applied to the power control of PV grid-connected inverter in this paper. In this way, the PV grid-connected inverter can transports both active power and reactive power to the distribution network....
Deployed software applications use log files to keep a record of system events. Log analysis provides support for system administrators to gain the knowledge of system health and behavior. As a result, the ability to efficiently search for patterns in historical events has become a major requirement for timely analysis. Enterprise systems today produce high volumes of log data, regularly in the order...
We present a high performance and memory efficient hardware implementation of matrix multiplication for dense matrices of any size on the FPGA devices. By applying a series of transformations and optimizations on the original serial algorithm, we can obtain an I/O and memory optimized block algorithm for matrix multiplication on FPGAs. A linear array of processing elements (PEs) is proposed to implement...
In this paper, we present an automatic synthesis framework to map loop nests to processor arrays with local memories on FPGAs. An affine transformation approach is firstly proposed to address space-time mapping problem. Then a data-driven architecture model is introduced to enable automatic generation of processor arrays by extracting this data-driven architecture model from transformed loop nests...
This paper presents our experience with exploiting fine-grained pipeline parallelism for wavefront computations on a multicore platform. Wavefront computations have been widely applied in many application areas such as scientific computing algorithms and dynamic programming algorithms. To exploit fine-grained parallelism on multicore platforms, the programmers must consider the problems of synchronization,...
Previous works have projected that the peak performance of FPGAs can outperform that of the general purpose processors. However, no work actually compares the performance between FPGAs and CPUs using the standard benchmarks such as the LINPACK benchmark. We propose and implement an FPGA-based hardware design of the LINPACK benchmark, the key step of which is LU decomposition with pivoting. We introduce...
Loop tiling is an effective loop transformation technique that tiles the iteration space of loop nests to improve the data locality. The appropriate data layout and transfer strategies are also important to assist loop tiling. This paper describes an approach to enhance data reuse and reduce off-chip memory access after loop tiling. Data tiles due to loop tiling may have overlapped elements, which...
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