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A finite element model which contains one sixth of the IGBT module based on a real test chip of IGBT module is established to investigate the temperature and stress distribution of different shape bonding wire. The finite element (FE) analysis which coupled electro-thermal and thermal-mechanical are conducted using commercial software ABAQUS. The thermal performance and stress distribution of IGBT...
Residual stress is the most concerned issue in wafer grinding process, because it affects wafer performance and can induce wafer warpage. In this paper, the residual stress in wafers machined by different processing parameters is measured by Raman Spectroscopy. The effects of wheel feed rate, wheel rotating speed and wafer rotating speed on residual stress are investigated. Radial distance as a dimensional...
As the demand of power converter for higher power density is increasing, bonding wire failure of IGBT module becomes more severe. Accordingly, it is of great significance to investigate the reliability of bonding wire under operating condition for improving the reliability of IGBT module. In this paper, the finite element model of IGBT module was established, and a two-step indirect coupling electro-thermal-mechanical...
Insulated gate bipolar transistor (IGBT) operates at high current, high power and repeated shock current conditions. Joule heating induced during high current conditions, subsequently raising the temperature of the IGBT module. In this paper, we carried out the DC power cycling test with the 200 A current condition. The temperature distribution and the temperature change process of the whole IGBT...
Through Silicon via (TSV) technology makes the stacked chip to achieve the shortest distance of interconnection in vertical direction (z direction). However, there are many challenges for TSV wafer processes. One of the challenges is TSV wafer backside grinding process. In this paper, a predictive model was introduced to calculate the normal grinding force, and a dynamic finite element modeling methodology...
In order to solve the problem of cutting temperature measurement during the QFN cutting separation process, the infrared thermal imager is used to measure the QFN cutting temperature under different conditions, which include: with cutting fluid, without cutting fluid, and different cutting speed of 300/600/900 rpm. Temperature measuring results show: when without cutting fluid, temperature almost...
We propose a simple and effective even-power fast algorithm to obtain scalable fringe precision in self-mixing interference. In this letter, the principle of the even-power fast algorithm is introduced in detail. The validity of the proposed algorithm is demonstrated by means of simulated signals and confirmed by experimental measurements at different vibration amplitudes. Without adding any additional...
Vibration reliability test for plastic ball grid array solder joints have been developed by performing vibration tests with constant G-level input excitation. A specially designed PBGA assembly with built-in daisy chain circuits was mounted on a printed circuit board as the test vehicle. The test vehicle was mounted on vibration shaker by four standoffs at the corner of the board. It was then excited...
Current densities of 1.5ASD and additive concentrations of 15ml/L were used to electroplate the copper into TSV to fabricate the test samples. The samples were annealed at 425°C for 30 minutes in a vacuum furnace with the heating rate of 10°C /min. The annealed samples were thermal cycled with temperature range (25∼325°C), heating & cooling rate (10 °C/min), dwell time of 2 min at the peak and...
Rotating grinding is the most commonly used technique in silicon wafer thinning, while it will induce edge chipping as wafer thickness decrease. This will lead to wafer breakage, and thus resulting in cost waste. This study investigates edge chipping of silicon wafers in rotating grinding. The study correlates edge chipping with grinding process parameters, such as wheel rotation speed, wafer rotation...
Thermal cycling reliability test and finite element analysis have been conducted for plastic ball grid array assembly with Sn63Pb37 solder. Based on the thermal cycling test results, a two-parameter Weibull distribution model was used to determine the characteristic time to failure of plastic ball grid array assembly. Besides, cross-sectioning and optical microscope examination were utilized to identify...
In the plastic ball grid array package (PBGA) assembly, there are many solder balls and copper pads. The whole packaging varies a lot in size. This multi-scale structure brings difficulties in building the finite element model. The paper refers a method to avoid difficulties by replacing the unconcern copper pad/solder mask layer with a homogenous material layer. The finite element method (FEM) is...
As the demand expanding for high electrical performance, high pin count and low cost, the copper pillar bump packaging has been extensively used in recent years. However, the drawback is that copper pillar bump can introduce high stress, especially on low-k chip. In this paper, finite element method was adopted to optimize the structure of copper pillar bump, aiming at relieving the stress of low-k...
Mechanical properties of electroplating copper (Cu) filled in the through silicon vias (TSVs) are critically important in the reliability assessment of TSV packages. In order to obtain its mechanical properties, such as Young’s modulus, hardness, and stress-strain relationship, wafers with TSVs are fabricated by a typical manufacturing process, and then nanoindentation tests are conducted to extract...
The thermal-mechanical reliability of the flip-chip with copper pillar bump is analyzed through finite element numerical simulation and Kriging response surface models optimization method. The results show that: the successive order of factors affecting the chip warpage is: die thickness, bump pitch, die thickness, substrate thickness, Cu Pillar height, Cu Pillar height, PI thickness, PI opening size;...
The effect of electroplating parameters (filling current density and additive concentration) on the copper in Through-Silicon-Via, abbreviated to TSV-Cu, protrusion during annealing is analyzed. Also, the influence of electro deposition parameters, and the annealing process on the TSV-Cu protrusion during thermal cycling are studied. The result shows that, the distribution of the TSV-Cu protrusion...
Three-dimensional (3D) integrated circuit (IC) technology is considered as the preferred More-than-Moore approach due to its capabilities of miniaturization, high density and multi-function. And through silicon via (TSV) is the key enabling technology of 3D integration. So now TSV is getting more and more attention. However, TSV manufacturing processes are still facing several challenges, one of which...
Through Silicon Via (TSV) has emerged as a good solution to provide high density interconnections in three-dimensional packaging interconnect technologies. However, the thermal-mechanical reliability is a big issue. When the TSV is subjected to thermal load, large stress and strain would be created at the interface of the materials because of the great mismatch of CTE. In this paper, an axi-symmetric...
Through silicon vias (TSVs) have been extensively studied because it is a key enabling technology for achieving three dimensional (3D) chip stacking and silicon interposer interconnection. The large mismatch between the coefficients of thermal expansion (CTE) of copper and silicon induces stress which is critical for the TSV reliability performance. This paper proposes analytical solutions of stress...
The silicon layer containing through silicon vias (TSVs) is considered as anisotropic fiber reinforced composite layer with different longitudinal and transversal properties. An analytical approach is presented to estimate the effective Young's modulus, Poisson's ratio and coefficient of thermal expansion (CTE) for composite layer. It shows that the TSVs have no significant influence on the deflection...
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