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In this paper, we propose a subthreshold SRAM cell structure which can be read differentially. The main advantage of the cell is its high read current while the static noise margin and power consumption are reasonable. The cell is suitable for high performance applications where the speed is of prime concern. To assess the efficiency of the proposed cell, we compare its characteristics to three subthreshold...
In this paper, a comparison between CNFET and Si-MOSFET SRAM cells at 32 nm technology node are presented. The designs are based on predictive technology model (PTM) for the Si-MOSFET cell and CNFET Stanford model for the CNFET cell. For practical reasons, in the CNFET case, the substrate of the entire chip is considered to be one node. The effect of the voltage of this node on improving the overall...
In this paper, we investigate the performance characteristic of CNFET inverter based on a new compact model. We consider temperature variation effects on the CNFET circuit performance implemented in a 32-nm technology. The results show in contrast to MOSFET sub-threshold current reduces in CNFET with temperature. So by using CNFET in high temperature applications we can obtain high speed and low leakage.
On-chip MOS decoupling capacitors (DECAPs) are widely used to reduce power supply noise. Designing DECAP in nanotechnology designs provides many challenges. In this paper first it is shown that all of these challenges are functions of the DECAP channel length. Then, we propose a method for optimizing the channel length of MOS DECAPs. The technique is applied to 45 nm and 32 nm technology nodes and...
In this paper, we investigate the temperature dependence of delay propagation characteristic of FinFET circuits. The study is performed on several digital circuits including inverter, NAND, NOR, XOR and full-adder implemented in a 32-nm FinFET technology. The results show that the speed of the FinFET circuits is enhanced when the temperature is increased. The temperature dependencies of the FinFET...
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