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In this paper, we present a fast low-power low-energy standard public-key cryptography processor for use in power/energy-limited applications. The proposed prime-field elliptic-curve cryptography hardware uses a modified Montgomery modular inverse algorithm to minimize the total calculation time and is completely flexible in terms of the field and curve parameters. The power consumption is minimized...
In this paper, two static random access memory (SRAM) cells that reduce the static power dissipation due to gate and subthreshold leakage currents are presented. The first cell structure results in reduced gate voltages for the NMOS pass transistors, and thus lowers the gate leakage current. It reduces the subthreshold leakage current by increasing the ground level during the idle (inactive) mode...
In this paper, a low-power high-performance logic style for low-voltage CMOS technologies is presented. The style is based on modifying a high-speed yet low-power logic family called feedthrough logic (FTL) style which has been previously proposed in the literature. The proposed style which is called parallel FTL (PFTL) overcomes the shortcoming of the FTL for low-voltage applications. To assess the...
In this paper, we propose a new and low-power architecture for synchronous ring counters which can noticeably reduce the switching activity of the conventional ring counters. To achieve the goal we partition the ring counter into some blocks for each of which we use a special clock gator. The Hot block (the block in which the '1' exists) is the only block the flip-flops of which are clocked. The delay...
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