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A 32 nm BEOL with PVD CuMn seedlayer and conventional PVD-TaN/Ta liner was fully characterized by fundamental, integrated, and reliability methods. CuMn was confirmed to have fundamental advantages over CuAl, such as higher electromigration (EM) reliability for the same Cu line resistance (R). Both low R and high reliability (EM, SM, and TDDB) were achieved. Improved extendibility of CuMn relative...
As the current-carrying capability of a copper line is reduced due to interconnect dimension shrinkage, self-aligned CoWP metal-cap has been reported to be helpful to improve degraded electromigration (EM) reliability. However, adoption of the metal cap in general further exacerbates the already problematic low-k dielectric TDDB reliability at 32nm and beyond. This paper provides a comprehensive study...
Major efforts are currently underway throughout the IC industry to develop the capability to integrate device chips by stacking them vertically and using through-silicon vias (TSVs). The resulting interconnect density, bandwidth, and compactness achievable by TSV technology exceed what is currently possible by other packaging approaches. Market-driven applications of TSV involving memory include multi-chip...
In this work, we demonstrate the capability of Ecmp to meet the 45 nm and 32 nm technology node requirements in terms of topography behavior, the related electrical spread, lithography DOF budget and ULK compatibility.
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