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The group-IV-based spintronics is extremely appealing, due to high compatibility with mainstream Si-based technology [1]. Since the discovery of giant magnetoresistance (MR) from Fe/Cr multilayers [2], extensive studies of Fe-based heterogeneous structures have been performed for spintronic applications. To sum up, taking into account the potential application of group-IV-based spintronics and the...
Strain techniques have been adopted and widely used in the advanced nodes since early 65nm for carrier mobility improvement. For PMOS, eSiGe incorporation in the SD is the process of choice to induce compressive strain in the channel for mobility improvement. To further lower the contact resistance, it is preferred to boost Boron concentration for pSD formed by eSiGe process. Normal implant process...
Technology challenges and solutions in the development and fabrication of high-density three dimensional (3D) chip integration structures have been investigated. Critical 3D integrated circuit (IC) enabling technologies, such as through silicon via (TSV), wiring and redistribution layer (RDL), wafer thinning and handling, micro-bump (μ-bump) processes and joining, that form the building blocks for...
The gate-all-around (GAA) silicon nanowire transistor (SNWT) is considered as one of the best candidates for ultimately scaled CMOS devices. This paper discusses the process impact on nanowire LER/LWR, as well as the impact of 2D nanowire LER on performance variation and degradation. And it is found that SNWTs, which is immune to channel RDF(random dopant fluctuation), exhibit SDE-RDF which is enhanced...
In this paper, a 200 nm n-channel inversion-type self-aligned In0.53Ga0.47As MOSFET with a Al2O3 gate oxide deposited by Atomic Layer Deposition (ALD) is demonstrated. Two ion implantation processes using silicon nitride side-wall are performed for the fabrication of the n-type source and drain regions. The 200 nm gate-length MOSFET with a gate oxide thickness of 8 nm features the transconductance...
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