The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper presents a power- and area-efficient three-stage amplifier suitable to drive high capacitive loads. The amplifier is compensated by a single Miller Capacitor and an additional feedforward stage. To improve the amplifier large signal transient response, the topology also includes an external feedforward path and a novel slew-rate enhancer section. Implemented in a 0.35-μm CMOS process, the...
This paper addresses a new compact low-power class-B buffer amplifier topology for large-size liquid crystal display applications. The proposed buffer achieves high-speed driving performance, draws a low quiescent current during static operation and offers a rail-to-rail common-mode input range. The circuit provides enhanced slewing capabilities with a limited power consumption by exploiting two current...
This work proposes and develops an original compensation approach for low-power three-stage operational transconductance amplifiers driving large capacitive loads. The proposed solution is based on the basic reversed nested Miller compensation and exploits a voltage buffer and two nulling resistors in the compensation network, along with a feedforward stage to improve slewing and settling performance...
This paper proposes and develops an original power-efficient reversed nested Miller compensation technique for low-power three-stage amplifiers driving large capacitive loads. The proposed approach exploits dual-active buffers in the compensation network, along with a feedforward gain stage providing enhanced speed performance. A well-defined design procedure for the compensation elements is also...
A frequency compensation technique for three- stage amplifiers is introduced. The proposed solution exploits only one Miller capacitor and a resistor in the compensation network. The straightness of the technique is used to design, using a standard CMOS 0.35-mum process, a 1.5-V OTA driving a 150-pF load capacitor. The dc current consumption is about 14 muA at DC and a 1.6-MHz gain-bandwidth product...
A novel frequency compensation technique for three-stage amplifiers is introduced. The proposed solution exploits two Miller capacitors, two resistors and an additional feedforward stage which can be implemented without entailing extra transistors. Design equations using the phase margin as design parameter are carried out. The technique is used to design, with a standard CMOS 0.35-mum process, a...
In this brief we propose a simple dynamic model of a Dickson voltage multiplier with N stages, which is obtained starting from the models previously proposed for less than 5 stages. The model allows increased insight into the dynamic behavior of these circuits and provides a valuable tool for determining a first version design.
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.