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Strain engineering has been in the heart of CMOS technology for over a decade. However, the effectiveness of conventional strain elements, such as stress liners, embedded S/D stressors, and stress memorization, is significantly reduced when device gate pitch is scaled below 100 nm as needed for 14nm node and beyond. Substrate strain engineering, where the channel itself is formed out of a strained...
SiC:Er2O3 films with different ratios of SiC to Er2O3 have been deposited on p-type Si substrates by the magnetron co-sputtering technique fully compatible with current Si processing technologies. 1.54 µm electroluminescence from the structure of indium tin oxide (ITO)/n+-Si/SiC:Er2O3/p-Si with suitable ratios of SiC to Er2O3 was measured under forward biases.
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