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In many high-speed parts of chips, latch-based circuits are used to enable time borrowing, where a block may take longer time than its nominal delay to complete its computation. This enables such circuits to attain high performance and yield. In [1] and [2], we focused on maximizing path delay fault coverage and proposed the first structural delay testing approach and the associated design-for-testability...
Sticky path-delay faults are path delay faults that are neither robustly nor non-robustly testable, but cannot be proven functionally unsensitizable. Better characterization of delay test quality requires a proper analysis of sticky path-delay faults. Furthermore, careful elimination of sticky path-delay faults contributes significantly to test development productivity and reduction of delay test...
In this paper, we propose an approach to generate vectors that invoke high delays. We first identify properties of different types of paths, especially sticky paths, i.e., paths that are functionally sensitizable but not even non-robustly testable. In particular, we show that it is impossible to guarantee detection of sticky path-delay faults. We then identify logic and timing conditions that are...
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