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This paper presents design of an all-digital fully-integrated 5th-order Gaussian pulse generator (PG) for full band (3.1GHz-10.6GHz) impulse radio ultra wideband (IR-UWB) transceiver SoC. The design is implemented in a foundry 0.18μm CMOS process. New FCC effective isotropic radiated power (EIRP) aware design technique is used to optimize the PG. Measurement shows peak pulse amplitude of 533mV at...
A high performance 22/20nm CMOS bulk FinFET achieves the best in-class N/P Ion values of 1200/1100 μA/μm for Ioff=100nA/μm at 1V. Excellent device electrostatic control is demonstrated for gate length (Lgate) down to 20nm. Dual-Epitaxy and multiple stressors are essential to boost the device performance. Dual workfunction (WF) with an advanced High-K/Metal gate (HK/MG) stack is deployed in an integration-friendly...
A 32nm RF SOC technology is developed with high-k/metal-gate triple-transistor architecture simultaneously offering devices with high performance and very low leakage to address advanced RF/mobile communications markets. A high performance NMOS achieves an fT of 420GHz. Concurrently, a low leakage 30pA/um NMOS achieves an fT of 218GHz. Deep-nwell/guard rings improves noise isolation by >50dB. High...
This paper reviews advances in new 3D electro-thermal modeling technique for ESD (electrostatic discharge) protection structures. New 3D ESD device modeling is critical to full-chip ESD protection circuit design synthesis, verification, optimization and prediction, especially for IC designs in sub 100 nm CMOS technologies.
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