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This paper presents a novel 24/36-GHz double conversion heterodyne architecture for IEEE 802.15.3c (60-GHz) applications. The selection of the first local oscillator frequency as 36-GHz gives rise to an intermediate frequency that yields significant cost advantage by reusing the 24-GHz architecture adopted by the automotive industry for both the receiver and transmitter second stage frequency translation...
In this paper, a novel input stage based on dynamic threshold voltage transistors (DTMOS) for low-voltage, low-power and low-noise operational amplifier has been described. Its input differential pair is based on the combination of DTMOS and composite transistors (self-cascode transistors). Under 1V supply voltage, input stages for operational amplifier that input differential pairs operate in three...
An ultra-wideband (UWB) 3.1- to 10.6-GHz low-noise amplifier (LNA) employing a common-gate stage for wideband input matching is presented in this paper. Designed in a commercial 0.18-mum 1.8-V standard RFCMOS technology, the proposed UWB LNA achieves fully on-chip circuit implementation, contributing to the realization of a single-chip CMOS UWB receiver. The proposed UWB LNA achieves 16.7plusmn0.8...
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