The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The diode-triggered silicon-controlled rectifier (DTSCR) is frequently used for low-voltage electrostatic discharge (ESD) protection applications, but such a device can exhibit two snapbacks and consequently can possess an undesirable large trigger voltage. This letter investigates the mechanism underlying the DTSCR's multiple triggering. An improved DTSCR for reducing the second trigger voltage and...
Three types of MOS-triggered SCR structures: Merged MOS-triggered SCR, compact MOS-triggered SCR and boundary-MOS-triggered SCR devices have been fabricated and compared in 0.13 μm CMOS process for on-chip ESD protection. TLP testing results show boundary-MOS-triggered SCR structures can achieve adjustable and lower switching voltage, smaller turn-on resistance, faster turn-on speed, the best ESD...
MOS-Triggered Silicon Controlled Rectifier(SCR) has been used as on chip Electrostatic Discharge (ESD) protection. However, the inherit slow turn-on speed is a major drawback of SCR. The compact MOS-Triggered SCR devices have been proposed and investigated in a 0.13μm CMOS process with the consideration of turn-on speed. From the test results, the turn on time of compact MOS-Triggered SCR has improved...
A novel substrate-trigger GGNMOS structure with increasing the substrate resistance and pumping substrate trigger current using the VDD bus line controlled PMOS is proposed and verified in 65 nm CMOS process. The trigger voltage can be significantly reduced to ~3 V to safely protect the ultrathin gate oxide. The proposed structure has lower overshoot voltage which is helpful to protect the ultrathin...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.