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A single chip receiver based on super-regeneration incorporates an on-chip slot antenna and digital received data synchronization. A capacitively-loaded standing-wave resonator improves energy efficiency. An all-digital PLL timing scheme synchronizes the received data clock. The prototype 5 GHz receiver, implemented in 0.13 mum CMOS, achieves a data rate of up to 1.2 Mb/s, dissipates 6.6 mW from a...
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