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This paper presents the design rationale and measured results of a low power, low jitter, PVT-stable FBAR-based RF synthesizer implemented in 0.13μm CMOS. A digitally controlled FBAR oscillator, tuned with a switched-capacitor array, provides 5800ppm of frequency tuning, sufficient to cover a wide range of manufacturing and temperature variations of an FBAR. An all-digital phase-locked loop (ADPLL)...
A ROM-less direct digital frequency synthesizer employing trigonometric quadruple angle formula is present in this paper. The worse case spectral purity is better than -130 dBc. The amplitude resolution is up to 13 bits, while the phase resolution is 12 bits. Neither any scaling table nor error correction tables are required. The maximum error is mathematically analyzed. The word length of each multiplier...
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