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Fault and fault model is the fundament of IC diagnosis. Fault model based on IDDT and its test is the hot issue of modern IC fault diagnosis at present. Open and short fault models of inverter, NAND gate, and SRAM of CMOS technology were built in this paper. In the experiments, we selected the deep sub-micron of 0.18 mum CMOS technology to simulate with HSPICE. The simulations of IDDT waveforms and...
A novel 50% duty-cycle corrector (DCC) of digital signal processing (DSP) systems, designed with a purely digital phase-blending technique, is presented in this paper. The novel features of the proposed DCC includes a higher reliability against process, voltage and temperature variation due to the use of the synchronous mirror delay (SMD) technique, no-skew output clock, and a much faster duty-cycle...
This paper presents a wideband circuit model of silicon-based interconnects for predicting their metallic and silicon substrate losses at higher frequencies. The skin and proximity effects in the structure are characterized using the partial element equivalent circuit (PEEC) method, and the parasitic parameters in silicon substrate are captured according to some analytical equations. Good agreements...
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