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An 8-bit 1.5GS/s 2-way two-step SAR ADC operating at 0.9V is presented in this paper. A low-skew demultiplexer circuit is proposed to synchronize the sampled signals of the two sub-ADCs with the edge of global clock. The sharing of the quarter clock phase generator leads to lower power consumption. A charge-sharing technique without any interstage residue amplifier not only makes the two-step SAR...
A comma detection and word alignment circuit is proposed for a 6.25-Gb/s SerDes. In order to achieve a high speed, a new architecture of combined parallel and pipelined is employed. Based on the proposed structure, a high speed comma detector is implemented using 0.18im CMOS technology. Post simulation result indicates that the circuit can operates up to 770MHz with a power consumption of 10.8 mW...
Aiming at the problem of the LCD controller accessing the frame memory exiting in the design of LCD controller, on the base of analyzing and comparing the two familiar solving schemes, a new one is put forward. A new type LCD controller is designed and realized by applying the scheme. The problem of conflict between reading and writing frame cache is solved through the time-division multiplexing technology;...
This paper proposes and implements a robot audition module which can detect voice activity, estimate sound source direction and enhance speech signal in a noisy environment. These algorithms are implemented on an embedded dual-core processor platform which includes a ARM subsystem and DSP subsystem. An eight-channel digital microphone array is also implemented for sound data acquisition. All the experiments...
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