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This paper describes the realization of an interconnect Delay Insensitive (DI) FPGA architecture with distributed asynchronous control. This architecture maintains the basic block structure of traditional FPGAs allowing the potential use of existing FPGA design tools in block design. This asynchronous FPGA architecture is mainly aimed at tolerating the unpredictable delay variations caused by process...
Asynchronous techniques have become more significant with continued scaling of VLSI technologies. This paper proposes an asynchronous FPGA architecture. Different from previous methods of introducing asynchrony into FPGAs, our method seeks to preserve the current FPGA cell structure as much as possible, whilst achieving delay insensitivity in the inter-cell interconnects. By using David Cells as the...
Multi-resource multi-client arbiters are becoming more important in on-chip systems because of the increasing significance of dynamic, run-time, allocation of various system performance resources such as power and computation and communication facilities. Arbiters, for example, can be used to limit the amount of concurrency for regulating voltage droops, and for balancing load and traffic. This paper...
To deal with the problem of maintaining variable data set in digital image processing, this paper brings forward a general hardware structure for linked-list. It is designed to accomplish the commonly used functions and some more complicated functions of the linked-list data structure. In order to fully utilize the limited memory resources in embedded hardware platform, we propose a memory recycle...
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