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In this paper, an on-chip eye opening monitor circuit has been proposed with 4 ps time and 4 mv voltage resolutions for analyzing signal integrity of on-chip high speed channel. The proposed eye opening monitor circuit can detect the maximum 6.4 Gbps data rate and give eye diagrams depending on on-chip high speed channel conditions. The performance of the proposed eye opening monitor circuit was verified...
Crosstalk induced in a meander delay line produces a significant amount of waveform distortion and data-dependent jitter at the output port. This paper introduces an interpretation of the eye-diagram distortion and the jitter generation mechanism based on a time-domain even- and odd-mode analysis of a coupled transmission line structure. From the proposed analysis, this paper proposes jitter-estimation...
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