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An all-digital fast-lock synchronous multi-phase clock generator is presented. By using a time-to-digital converter for fast-lock operation and delay measurement, the proposed multi-phase clock generator generates four-phase clocks and synchronizes the reference clock with the output clock within 45 cycles. Furthermore, the clock generator uses a fine binary scheme and de-skewing circuit for fine...
This paper presents a fast lock all-digital delay-locked loop (ADDLL) with a wide range and high resolution all-digital duty cycle corrector (ADDCC), which achieves low jitter, fast lock time, and accurate 50% duty cycle correction with a clock-synchronized delay (CSD) and time-to-digital converter (TDC) schemes. The ADDLL uses a self-calibration scheme to reduce the phase error and jitter, and a...
A 6-bit, 1.6-GS/s, flash ADC with a low-power architecture is presented. The proposed low-power architecture based on an analog input pre-processing method reduces the total number of comparators to almost two-thirds of that required in a conventional 6-bit, flash ADC. The advantages of the analog input pre-processing method include the low power consumption and small area due to the reduced number...
A 31 mW, 10-bit 100 MS/s pipelined ADC has been developed. The proposed ADC achieves low power consumption, high noise immunity, and small area by employing a new opamp sharing technique that switches the summing node in an MDAC and a current source with a PVT condition detector. The ADC shows a DNL of less than 0.48 LSB and an INL of less than 0.95 LSB. Also, a SNDR of 56.2 dB is measured with a...
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