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A transition-code based method is proposed to reduce the linearity testing time of pipelined analog-to-digital converters (ADCs). By employing specific architecture-dependent rules, only a few specific transition codes need to be measured to accomplish the accurate linearity test of a pipelined ADC. In addition, a simple digital Design-for-Test (DfT) circuit is proposed to help correctly detect transition...
In our previous work, the reduced code based method has been proposed to significantly reduce the linearity test time of a pipelined ADC. The digital error correction (DEC) technique is extensively employed in a pipelined ADC. A pipelined ADC with this technique can tolerate large comparator offset without degrading the ADC linearity. However, in this paper, we find that comparator offsets would cause...
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