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Porous low-k dielectrics reliability in interconnect is a major concern for sub 45 nm technology nodes. Low-k dielectric ageing characterization during stress is becoming a key point to improve low-k interconnect robustness. In this context, the leakage and especially the capacitance shifts under electrical stress are analyzed in this paper. Four dielectric ageing mechanisms potentially responsible...
This work analyses electromigration and dielectric lifetimes of 45 nm node CMOS interconnects. Reliability mechanisms and failure modes are discussed considering, on one hand, the interconnect materials and processes steps, and on the other hand scaling issues. Robust reliability performance meeting the required products target is actually obtained with process integration schemes used for the 45...
SiOCH low-k dielectrics introduction in copper interconnects associated to the critical dimensions reduction in sub 45 nm technology nodes is a challenge for reliability engineers. Circuit wear-out linked to low-k dielectric breakdown is now becoming a major concern. With the reduction of the line to line spacing, the control of the copper line topology is becoming a first order parameter governing...
SiOCH low-k dielectrics introduction in copper interconnects associated to the critical dimensions reduction in sub-45-nm node technologies is a challenge for reliability engineers. Circuit wear-out linked to low-k dielectric breakdown is now becoming a major concern. With line-to-line spacing reduction, the control of the line shape and of the spacing uniformity within a wafer is becoming first-order...
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