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We have discovered that processors can experience a super-linear increase in detected unrecoverable errors (DUE) when the write-back L2 cache is doubled in size. This paper explains how an increase in the cache tag's Architectural Vulnerability Factor or AVF caused such a super-linear increase in the DUE rate. AVF expresses the fraction of faults that become user-visible errors. Our hypothesis is...
The design of space-efficient support hardware for built-in self-testing (BIST) is of critical importance in the synthesis of cores-based system-on-chips (SOCs). This paper reports on further studies on a space compression technique recently developed by the authors that facilitates designing such circuits using pseudorandom and compact test sets, with the basic objective of reducing the storage requirements...
In this paper we present an algorithm for allocating scan flops to scan chains based on the placement information of flops. The objective of the algorithm is to reduce the scan wire length, the number of level shifters and the number of lockup latches in the scan path. The algorithm uses a novel partitioning based approach to allocate and order the scan flops for a particular scan chain. The scan...
This paper presents an approach to fault simulation in the particular context of ISCAS 85 combinational benchmark circuits based on hardware description language (HDL) specification of their gate level netlists. The approach, exploiting the existing force and release features available in Verilog, builds an effective fault simulator by properly utilizing Verilog syntax with application to fault modeling...
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