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We present a new ETSOI CMOS integration scheme. The new process flow incorporates all benefits from our previous unipolar work. Only a single mask level is required to form raised source/drain (RSD) and extensions for both NFET and PFET. Another new feature of this work is the incorporation of two strain techniques to boost performance, (1) Si:C RSD for NFET and SiGe RSD for PFET, and (2) enhanced...
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