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In this paper, we aim to present a surface potential based model for GaN High Electron Mobility Transistors. The analytical model is computationally efficient and can be accurately used for DC and RF predictions. It includes various effects of velocity saturation, access region resistance, temperature, gate current and noise.
In this paper, a novel VLSI architecture for one dimensional Walsh-Hadamard transform (WHT) is proposed. The core of the architecture is the HVMA (Hadamard Vector Merging Adder) that adds the products of input data words and transform (Hadamard) matrix elements in parallel using a (4:2) compressor based carry-save tree structure. The core also exploits the Hadamard matrix's property of equal distribution...
Watching movies has been one of the oldest sources of recreation. Standing in long queues for availing tickets has been a problem though. In the present day scenario the possibility of terrorist attacks in movie halls has also increased. In our paper, we have described a novel scheme how the movies can be seen in a multiplex without standing in long queues. Also, the security of multiplexes can also...
Masking of gates is one of the most popular techniques to prevent differential power analysis (DPA) of AES S-boxes. However due to the presence of glitches in circuits even masked circuits leak side-channel information. Motivated by this fact, we proposed a balanced masked multiplier where the inputs are synchronized either by sequential components or controlled AND logic, that can be a possible solution...
Design considerations for robustness with respect to variations and low-power operations typically impose contradictory design requirements. Low-power design techniques such as voltage scaling, dual- , etc., can have a large negative impact on parametric yield. In this paper, we propose a novel paradigm for low-power variation-tolerant circuit design called critical path isolation for timing adaptiveness...
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