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Recently, researchers are targeting low-power consumption, and integrating more blocks on-chip. This paper proposes a 1GS/s 6-bit time-based analog-to-digital converter (T-ADC) for front-end receivers. This T-ADC eliminates the preprocessing analog blocks, and reduces power consumption by removing the power-hungry sample and hold circuit. A prototype of the proposed T-ADC is implemented in 65nm CMOS...
An ultra-low power voltage-to-time converter (VTC) circuit is proposed. The VTC circuit is compatible with wide range of applications (i.e. sensors, integrated DC-DC voltage converters) especially for time-based analog-to-digital converters (T-ADCs). In T-ADCs, the input voltage signal is first converted into a delay pulse using the VTC circuit, then this delay signal is converted into a digital code...
This paper investigates various implementation techniques of neural amplifiers with emphasis on their design performance metrics and trade-offs such as gain, noise, power consumption, and area. The proposed comparative analysis covers the recently published neural amplifiers in the literature, and proposes a basic optimization method for these amplifiers. These amplifiers are redesigned using UMC...
In this paper, a leakage power reduction technique for field-programmable gate arrays (FPGAs) is proposed based on the state dependency property of leakage power. A pin reordering algorithm is proposed, where the subthreshold and gate leakage power components are taken into consideration to find the lowest leakage state for the FPGA pass-transistor multiplexers in the logic and routing resources without...
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