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This paper proposed a new algorithm for modeling and simulation of interconnect circuit in nanometer very large scale integration (VLSI) design considering manufacturing process variations. The approach is based on the existing passive reduced-order interconnect macromodeling algorithm (PRIMA). By satisfying the constraints of PRIMA, both macromodel stability and passivity are preserved, so that overall...
In this tutorial, we will shed some light on an inductive extraction and compact modeling of inductively coupled interconnects, especially in the presence of unavoidable fabrication variations in the technology of 90 nm and below. The tutorial consists of two parts. The first part of the tutorial will describe the existing partial element equitant circuit (PEEC) based inductance extraction methods,...
In this paper, we propose a novel on-chip voltage drop reduction technique for on-chip power delivery networks of VLSI systems in the presence of variational leakage current sources. The new method inserts decoupling capacitors (decaps) into the power grid networks to reduce the voltage fluctuation. The optimization is based on sensitivity-based conjugate gradientmethod and sequence of linear programming...
As the technology scales into 90 nm and below, process-induced variations become more pronounced. In this paper, we propose an efficient stochastic method for analyzing the voltage drop variations of on-chip power grid networks, considering log-normal leakage current variations with spatial correlation. The new analysis is based on the Hermite polynomial chaos (PC) representation of random processes...
In this paper, we propose an efficient algorithm to reduce the voltage noises for on-chip power/ground (P/G) networks of VLSI. The new method is based on the sequence of linear programming (SLP) method as the optimization engine and a localized scheme via partitioning for dealing with large circuits. We show that by directly optimizing the decap area as the objective function and using the time-domain...
This paper proposes a fast decoupling capacitance (decap) allocation and budgeting algorithm for both early stage decap estimation and later stage decap minimization in today's very large scale integration physical design. The new method is based on a sensitivity-based conjugate gradient (CG) approach. But several new techniques that significantly improve the efficiency of the optimization process...
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