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Bandwidth is always one of the bottlenecks in system-on-a-chip (SoC) systems. In this paper, we propose an efficient architectural design in analyzing the bandwidth of each component in an H.264 design. We decompose the entire H.264 system bandwidths into several modules with predictable coefficients. The derived equations may help designers understand the real cost of each hardware component, thus...
This paper proposed a new algorithm for modeling and simulation of interconnect circuit in nanometer very large scale integration (VLSI) design considering manufacturing process variations. The approach is based on the existing passive reduced-order interconnect macromodeling algorithm (PRIMA). By satisfying the constraints of PRIMA, both macromodel stability and passivity are preserved, so that overall...
In this tutorial, we will shed some light on an inductive extraction and compact modeling of inductively coupled interconnects, especially in the presence of unavoidable fabrication variations in the technology of 90 nm and below. The tutorial consists of two parts. The first part of the tutorial will describe the existing partial element equitant circuit (PEEC) based inductance extraction methods,...
In this paper, we propose a new statistical model order reduction technique called SSMOR method, that is suitable for considering both intra-die and inter-die process variations. The SSMOR generates order reduced variational models from the original variational circuits. The reduced model can be used for fast statistical performance analysis of interconnect circuits with variational power sources...
In this paper, we propose an efficient algorithm to reduce the voltage noises for on-chip power/ground (P/G) networks of VLSI. The new method is based on the sequence of linear programming (SLP) method as the optimization engine and a localized scheme via partitioning for dealing with large circuits. We show that by directly optimizing the decap area as the objective function and using the time-domain...
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