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The construction and design process of a high-resolution time-interval measuring system implemented in a SRAM-based FPGA device is discussed in this paper. The TDC can increase the precision on the measurement by interpolating time within the system clock cycle. A two step phase interpolation has been constructed, one based on the phase information delivered by the VIRTEX-5 Digital Clock Manager (DCM)...
The construction and design process of two high-resolution time-interval measuring systems implemented in a SRAM-based FPGA device is discussed in this paper. The two TDCs can increase the precision on the measurement by interpolating time within the system clock cycle. In order to perform fine time measurement two different architectures have been realized. The first one uses dedicated carry lines...
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