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This paper introduces a novel energy efficient architecture for a turbo decoder using quadratic permutation polynomial (QPP) interleaver The Add Compare Select Offset (ACSO) unit of the maximum a posteriori probability (MAP) decoder, has been pipelined to a depth of four to reduce the critical path delay and increase the operating clock frequency and throughput as a consequence. The present turbo...
The work presented in this paper details an efficient architecture of a pipelined parallel turbo decoder utilizing contention free interleaver. Pipeline technique has been applied to reduce the critical path delay associated to the add compare select Offset (ACSO) unit so as to increase the operating clock frequency. The computational core of the complex maximum a posteriori probability (MAP) decoder...
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