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Target and anomaly detection are important techniques for remotely sensed hyperspectral data interpretation. Due to the high dimensionality of hyperspectral data and the large computational complexity associated to processing algorithms, developing fast techniques for target and anomaly detection has received considerable attention in recent years. Although several high-performance architectures have...
Endmember extraction is a very important technique in hyperspectral unmixing. Due to the fact that more applications require real or near real-time processing capabilities, high performance computing based on field-programmable gate array (FPGA) for endmember extraction has received considerable interest in recent years. In this paper, we propose a real-time implementation of maximum volume algorithms...
In this paper, we introduced a hardware acceleration coprocessor design of HIMAC 2.0 in HINOC 2.0 system. The main function of HIMAC 2.0 have been detailed and compared with corresponding part of HINOC 1.0. By building the self-testing platform and designing the test scheme, the design, which has been simulated and has passed the FPGA verification, realizes 1Gbps data transmission between HIMAC 2...
Target detection is an important topic for extracting information from hyperspectral imagery. Due to the high computational complexity, developing fast target detection algorithm has received considerable interest, specifically to take advantage of field-programmable gate array (FPGA) architecture in hardware implementation. In this paper, a novel streaming background statistics (SBS) method is used...
The tag sorting circuit in Weighted Fair Queuing (WFQ) is crucial to the Quality of Service (QoS). In this paper, we present a kind of optimized hardware architecture for fast tag sorting, which consists of one-hot encoding and leading zero counting. The architecture is parallel and pipelining. It is implemented using FPGA technology. In comparison with the traditional comparator-tree-based architecture,...
To meet the requirement of high-speed data processing of complicated system with multi-sensor inputs and multi-controller outputs, an embedded ARM+FPGA +DSP multiprocessor platform is designed, which is characterized by synchronous cooperation and mutual exchange of shared data. ARM completes interface expansion and task scheduling configuring peripheral interfaces including RS422, CAN and RJ45, and...
The increasing system resources available on field-programmable gate arrays (FPGA) enable the integration of complex system on one programmable chip. This paper focuses on the design and implementation of a hierarchy-bus based multi-processor system-on-chip (MPSoC) integrating 4 ARM processors on FPGA. Experimental results had been obtained running at 60MHz with total area requiring 34% adaptive look-up...
Hardware/software (hw/sw) partitioning is a critical step in the co-design, it directly affects the system performance largely. Targeting the shortcomings existed in the traditional algorithms, in this paper a guiding function based greedy partitioning algorithm (GFBGPA) is presented. The algorithm especially aims at the parameterized FPGA coprocessors architecture. The guiding function is determined...
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