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A 576 Mb DRAM is implemented with 16 serial links at 10.3125Gbps. Using careful memory/SerDes/package co-design, the system achieves 14.5ns latency and 24.75GByte/s read/write bandwidth. It achieves SRAM-like random access by using logic-compatible 65nm GP embedded DRAM and small 36 Kb sub-arrays with hidden refresh.
Traditional architecture design approaches hide hardware uncertainties from the software stack through over-design, which is often expensive in terms of power consumption. The recently proposed quantitative alternative of stochastic computing requires circuits and processors to be correct only probabilistically and use less power. In this paper, we present the first step towards a theory of stochastic...
Full scan based design technique is widely used to alleviate the complexity of test generation for sequential circuits. However, this approach leads to substantial increase in test application time, because of serial loading of vectors. Although BIST based approaches offer faster testing, they usually suffer from low fault coverage. In this paper, we propose a hybrid test architecture, which achieves...
Transistor aging results in circuit delay degradation over time,and is a growing concern for future systems. On-line circuit failure prediction, together with on-line self-test, can overcome transistor aging challenges for robust systems with built-in self-healing. Effective circuit failure prediction requires very thorough testing to estimate the amount of aging in various parts of a large design...
Circuit failure prediction is used to predict occurrences of circuit failures, during system operation, before errors appear in system data and states. This technique is applicable for overcoming major scaled-CMOS reliability challenges posed by aging mechanisms such as Negative-Bias-Temperature-Instability (NBTI). This is possible because of the gradual nature of degradation associated with such...
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