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In this work, we study dynamic characteristic of digital CMOS circuits of 16-nm HKMG bulk FinFET devices by optimizing fabrication windows of inline parameters. Key process parameters are ranked according to integrated circuit quiescent current (IDDQ) and delay of ring oscillators. IDDQ and delay are affected by the dual gate-spacer, the source/drain (S/D) proximity, the S/D depth, and the S/D implant...
This paper reports a systematic method to discover and optimize key fabrication in-line process of 16-nm high-$ {\kappa }$ metal gate bulk FinFET to improve device’s performance and variability. The sensitivity analysis is utilized to prioritize key in-line process parameters which significantly boost device’s performance and effectively reduce its variations. To extract hidden correlations among...
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