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The MapReduce processing framework is unaware of the property of underlying datasets. For ordered datasets (e.g., time-series data), in which records have been already sorted, MapReduce still performs unnecessary sorting operations during its execution. It directly results in a significant increase of execution time, as sorting a large volume of data is time-consuming. In this paper, we propose a...
Transactional memory (TM) is a new shared resource synchronization mechanism which was proposed to ease the difficulty of parallel programming. Currently, most hardware transactional memory systems leverages the extended directory based cache coherence protocol to resolve transaction conflicts; seldom research has been conducted to extend a snoopy coherence based chip multi-processor with TM support...
RFID application becomes the focus recently. As an automatic identification technology, RFID has many advantages over traditional one like barcode. It does bring about tremendous changes, and also face lots of barriers during investment. In this paper, we integrate technology risk, IT risk and RFID risk, develop a RFID risk factor framework with analogy method, and find out the relationship between...
For the problems that MPlayer encountered when decoding high definition video on the embedded platform of Intel's CE3100, a novel dual-core player is designed according to the features of CE3100. The dual-core player includes one soft core player based on software decoder and one hard core player based on hardware decoder. Then, a main control center is introduced in the front of the player. The control...
Supporting unbounded transactions and operating system (OS) are two notable challenges that need to be efficiently resolved by practically accepted hardware transaction memory (HTM) systems. Current proposals that heavily rely on traditional cache system to handle version management or conflict detection support poorly to resolve these two challenges. Traditional approach brings either unavoidable...
Recent years, it has been a hot research topic on providing efficient and unbounded transactional memory support through hybrid hardware and software approach. Yet, current proposed systems which buffer transactional data in traditional data cache have high overhead and design complexity. In this paper, we propose a new design approach to build hybrid transactional memory system. Our approach adds...
Transactional memory (TM) provides efficient, easy, deadlock-free parallel programming model for today's multicore-ubiquitous hardware platform. Implementation of TM needs to guarantee that the transaction is executed atomically and in isolation. Our paper proposes an efficient and unbounded hybrid-mode TM system with strong isolation guarantee, called HybridTCache. HybridTCache optimizes the common...
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