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As an alternative to radio-frequency (RF) communications, optical wireless communications (OWC) can support high data rates and low power operations while providing good jamming resistance. Our focus in this paper is on deep ultraviolet (UV) outdoor communications (UVOC) where solar blind and non-line-of-sight operations are attractive. Light beams from UV LED arrays serve as information carriers...
Several regular parallel trees have been proposed over the years to optimize logic depth, area, fan-out and interconnect count for logic circuits. In this paper, we propose a comparative study of different parallel prefix trees used in the design of a new end-around carry (EAC) adder targeting FPGA technology. This new adder is based on the fast 128-bit binary floating-point EAC adder which has been...
Delay dependent decentralized robust H∞ control for a class of interconnected large-scale systems is considered. The time-delays are assumed as time-varying, and exist in interconnected and measurement output matrices. The decentralized output feedback H∞ controllers are designed. Combining the Lyapunov-Krasovskii functional approach and the delay integral inequality of matrices, the delay dependent...
Wide-area distribution raises significant performance problems for traditional query processing techniques as data access becomes less predictable due to link congestion, load imbalances, and temporary outages. Non-blocking joining query execution is a promising approach to coping with unpredictability in such environments because of reactively scheduling background processing. Classical non-blocking...
In data streams or Web scenario at highly variable and unpredictable rates, most fast join algorithms to date rely upon shifting to external join stage as soon as possible when blocked in order to enhance efficiency. But they have trouble with the following issues: the limit of external join and practical executing time. Classical progressive two-way joining technique based on hash, however, fail...
4:1 multiplexers (Muxs) and 1:4 demultiplexers (DeMuxs) are always the bottleneck in the GHz serializer/deserializer (SerDes) implementation. This paper discusses the design of the 60 Gb/s 4:1 Mux and 1:4 DeMux with the 0.18 mum silicon germanium (SiGe) BiCMOS technology. The Mux and DeMux are controlled by a quarter clock that significantly reduces the clock frequency and relaxes the circuit design...
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