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This article investigates pin accessibility problem of standard cells designed with a sub-20nm technology. The 15nm open cell library from NanGate and three of its variants with a reduced number of access points per pin based on FreePDK15 are used for our study. Our experiments show that a standard cell library is viable when the number of access points per pin is not less than three.
This paper proposes a two-stage transistor routing approach that synergizes the merits of channel routing and integer linear programming for CMOS standard cells. It can route 185 cells in 611 seconds. About 21% of cells obtained by our approach have smaller wire length than their handcrafted counterparts. Only 11% of cells use more vias than their handcrafted counterparts. Our router completes routing...
This paper presents an integer linear programming approach to transistor placement problem for CMOS standard cells with objectives of minimizing cell width, wiring density, wiring length, diffusion contour roughness, and misalignments of common ploy gates. Our approach considers transistor pairing and transistor placement simultaneously. It can achieve a smaller number of transistor chains than the...
This article presents a router, called Rover II, for via-configurable structured ASIC with mixed standard cells and relocatable IPs. Rover II extends the work of Rover and incorporates a porting of NTHU-Route 2.0 and NCTU-GR global routers. Experimental results show that Rover II can successfully route a via-configurable structured ASIC with standard cells and IPs under different routing fabrics....
A structured application-specific integrated circuit (ASIC) has prefabricated yet configurable logic block arrays. We investigate some important via-configurable logic block (VCLB) design issues. We particularly focus on creating a VCLB layout that enables a standard cell like design. We propose the VCLB composability concept which enables us to use multiple VCLB instances to realize a complex logic...
A structured ASIC has some arrays of pre-fabricated yet configurable logic blocks (CLBs) with/without a regular routing fabric. In this paper, we propose a standard cell like via-configurable logic block (VCLB). We design a 0.18 um standard cell library based on our VCLB and establish a design flow using as many commercial tools as possible. We also propose a method to evaluate the viability of a...
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