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This paper proposes a method to explore the design space of FinFETs with double fin heights. Our study shows that if one fin height is sufficiently larger than the other and the greatest common divisor of their equivalent transistor widths is small, the fin height pair will incur less width quantization effect and lead to better area efficiency. We design a standard cell library based on this technology...
Deduplication technology has been increasingly used to reduce the primary storage cost. In practice, it often causes additional on-disk fragmentation that impairs the reading performance. Existing deduplication algorithms mainly focus on the static data layout design so that the random I/O requests are largely avoided and the harmful effect can be alleviated. However, our trace-driven emulations show...
This paper proposes a two-stage transistor routing approach that synergizes the merits of channel routing and integer linear programming for CMOS standard cells. It can route 185 cells in 611 seconds. About 21% of cells obtained by our approach have smaller wire length than their handcrafted counterparts. Only 11% of cells use more vias than their handcrafted counterparts. Our router completes routing...
C-RAN, i.e., Cloud-Radio Access Network, is a new cellular network architecture for the future mobile network infrastructure. It is proposed to provide a possible solution for operators to construct mobile access networks in a cost-effective manner. Different from traditional cellular network architectures that are built with many stand-alone base stations (BSs), C-RAN is now viewed as an architecture...
Deduplication technology has been increasingly used to reduce the storage cost. In practice, it often causes additional on-disk fragments that impair the reading performance. To reduce the impact of fragments, traditional thought of defragmentation that reallocating files on-disk to achieve contiguous layout has been widely used in many operating systems. Unfortunately, file defragmentation is highly...
A structured application-specific integrated circuit (ASIC) has prefabricated yet configurable logic block arrays. We investigate some important via-configurable logic block (VCLB) design issues. We particularly focus on creating a VCLB layout that enables a standard cell like design. We propose the VCLB composability concept which enables us to use multiple VCLB instances to realize a complex logic...
This paper presents a simple method for design and analysis of a via-configurable routing fabric formed by an array of routing fabric blocks (RFBs). The method simply probes into an RFB rather than resorts to full-chip routing to collect some statistics for a metric used to qualify the RFB. We find that the trade-off between wire length and via count is a good metric. This metric has been validated...
Much recent research work seeks to turn off servers and redirect I/O load for energy efficiency under low utilization period, but most of them are highly constrained by data layout policy. There are two widely used replica placement schemes. One is sequential data layout policy like in Chained Declustering, which allows to power down a large fraction of nodes without disrupting data availability,...
Structured ASIC is a well-developed technology that enables a shorter design Turn-Around-Time (TAT) as well as less non-recurring-engineering (NRE) cost for very deep submicron designs. Since 2003, Faraday technology has developed its own structured ASIC solutions. Based on its own competitive technology architecture, Faraday has proposed platform-based SoC solutions and realized more than 100 customer...
In this paper we propose a synergetic approach that integrates router design and cell library engineering for improving post-routing via1 (via between M1 and M2) doubling rate at pins. We develop a double-via (DV) aware multilevel router to exploit the via1 doubling possibilities provided to the cells in a conventional as well as a DV-driven cell library. Compared to a non-DV-aware router using a...
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