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The main challenge of Low Temperature (LT) Solid Phase Epitaxy (SPE) is the dopant deactivation during post activation anneal. For the first time, we demonstrate that, for LT-SPE activated Boron (B) on thin SOI substrates, B deactivation can be well controlled during post anneal at 400 °C–600 °C. This is achieved by locating the preamorphization induced end of range defects close to the Buried OXide...
In this paper, we analyze the performance impact of different number of Through Silicon Vias (TSVs) in 3D Network-on-Chip (NoC). The adoption of a 3D NoC design depends on the performance and manufacturing cost of the chip. Therefore, a study of the placement of the TSV, that connects different layers of a 3D chip, is crucial. A 64-core 3D NoC is modeled based on state-of-the-art 2D chips. We discuss...
For the first time, 3D sequential integration is demonstrated down to LG=50nm. Molecular bonding is used to design a perfect a top active layer (thickness control, cristallinity) and a low Thermal Budget (TB) top FET (600°C) has been developed for bottom FET preservation. We demonstrate that this integration is viable for bottom and top MOSFETs with advanced LG. Additionally the low TB process compared...
Network-on-Chip (NoC) has become a widely accepted on-chip communication architecture which provides a promising solution to integrate a large number of components on a single chip. However, with the increasingly higher performance demands for on-chip systems, NoCs are facing several critical challenges such as wire delay and power consumption. Therefore, in this paper, we explore different cache...
A scheme for positioning swimmers using underwater acoustic networks is proposed. The design and the performance of such a network are presented. Owing to its high accuracy, the spherical interpolation approach is employed as the positioning algorithm. The configuration of the network, namely, the arrangement of anchor nodes in the swimming pool, is optimized to achieve the highest accuracy with the...
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