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The main challenge of Low Temperature (LT) Solid Phase Epitaxy (SPE) is the dopant deactivation during post activation anneal. For the first time, we demonstrate that, for LT-SPE activated Boron (B) on thin SOI substrates, B deactivation can be well controlled during post anneal at 400 °C–600 °C. This is achieved by locating the preamorphization induced end of range defects close to the Buried OXide...
For the first time, low temperature (LT) anneal at 625°C has been demonstrated for dopants activation enabling similar ION/IOFF trade-off as standard spike anneal (>1000°C), down to 30nm gate length (LG) for both n&p FETs. Similar short channel effect control has been achieved in LT n&p FETs as its high temperture (HT) counterparts. Influence of dopant implant tilt on LT device performance...
For the first time, 3D sequential integration is demonstrated down to LG=50nm. Molecular bonding is used to design a perfect a top active layer (thickness control, cristallinity) and a low Thermal Budget (TB) top FET (600°C) has been developed for bottom FET preservation. We demonstrate that this integration is viable for bottom and top MOSFETs with advanced LG. Additionally the low TB process compared...
22nm node Si SOI Coplanar “N Channel Vertical Dual Carrier Field Effect Transistors” (VDCFET) and its SOC with effective channel length less than 10nm for communication applications are presented.
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