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A general procedure to calculate the stability of the multiport memory cell is proposed. Noise margins of the 4-port and 8-port SRAM cell are studied. A novel 8-port memory cell is proposed to reduce the read access time.
A general procedure to calculate the stability of the multiport memory cell is proposed. Four novel architectures of the 8-port memory cell are introduced to improve the access time. With the same read access time and silicon area for all the designs, the proposed 6-inverter memory cell has the maximum noise margin.
We extend our previous work on delay estimation with a piecewise linear model and propose efficient formulae for power estimation including short-circuit power, dynamic power, and leakage power. Our piecewise linear model is a modified switched-resistor model considering transistor saturation current with a linearized BSIM3 capacitance model, which allows to compute energy and output slopes for static...
A piecewise linear delay model is accurate to within plusmn10% of SPICE over a wide range of the input transition time. Model accuracy has improved by taking into account the effect of the input slope and short circuit current. Comparisons with SPICE simulation has been observed in several test circuits.
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