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In this work, the progressive breakdown (PBD) phase and non-Weibull final failure distributions of multi layer high-k and SiO2 gate dielectric were investigated by voltage ramp stress (VRS) technique. A new hybrid two-stage constant voltage stress/voltage ramp stress methodology was developed to exclusively evaluate the PBD phase. Then the VRS technique was applied to investigate the non-Weibull failure...
A cell-based analytical percolation model recently proposed for the dielectric breakdown (BD) of high-K stack gate dielectrics is reformulated in terms of competing local percolation paths. The model is equivalent to kinetic Monte Carlo implementation of percolation and it is shown to be consistent with large sample size statistical data. This is a physics-based picture that predicts the scaling of...
High temperature RTO (Rapid Thermal Oxidation) process can get good quality but growth rate was too fast to get a controllable ultra-thin SiO2 as interfacial layer (IL) for high-K gate dielectrics application. In this paper, we investigated the physical and electrical properties of IL film obtained by different oxidation gas ratio, temperature, pressure. We found high temperature (>1080C) and hydrogen...
We have developed a low leakage and highly reliable SiON gate dielectrics by using novel low temperature deposition of chlorine-enriched silicon nitride upon a thin oxide. This method can achieve higher top-to-bottom nitrogen concentration ratio and keep nitrogen peak toward top surface. It was found that the low temperature Si3N4 deposition technique can form a high nitrogen percentage SiON (>...
We have investigated the precursor effect of La2O3 cap layers on Vfb tuning and EOT reduction in SiO2/HfO2/TiN gate stacks. The Vfb tuning and EOT reduction correlate with the intermixing of La2O3 and HfO2 dielectrics which forms dipoles at the lower interface between HfO2 and SiO2 IL and the diffusion of La and Hf atoms to the SiO2 IL. The use of La(fAMD)3 precursor for the La2O3 cap layer deposition...
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