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Recently, a tetragonal-like phase BiFeO3 (BFO) has been made by utilizing highly mismatched LaAlO3 (LAO)[1]. However, a significant contribution from the leakage current make great difficulty for a direct experimental observation of the ferroelectric hysteresis loop [1]. Here, ferroelectric BaTiO3 (BTO) was epitaxially grown on T-phase BFO/BTO (i.e., BFO film grown on a (001) oriented LAO substrate)...
This paper presents the analysis of the substrate leakage current to anode current ratio of the 700V n-type lateral IGBT with quasi-vertical DMOSFET (QVDMOS) fabricated with junction isolation technology. To improve the substrate leakage, a p-type buried layer (BLP) is inserted between the n-type drift region and the n-type buried layer (BLN). A junction isolated p-region, which is connected to the...
Next generation flip chip package with <100um fine bump pitch is developed in a cost effective Bump-on-Trace (BOT) package structure for 28nm Si technology node. This is foreseen to be a mainstream for mobile applications in next generations. The key challenges of this new technology include warpage control of molded underfill (MUF) for < 4 mils of thin die, packaging yield due to finer pitch...
The key technology challenges and solutions in the packaging and assembly of large dies and/or fine pitch on organic substrates for both the 40 and 28 nm technology nodes are reported. Both eutectic PbSn, Pb-free solders, and Cu pillar bumps were used in the flip chip packages. The key challenge of chip-package-integrations (CPI) due to the use of fragile extreme low-k (ELK) dielectric materials in...
On-body communication is of increasing interest for a number of applications, such as medical-sensor networks, emergency-service workers, and personal communications. This paper reviews 60 GHz on-body communication and its benefits and challenges. Two novel low profile high gain, end-fire wearable antennas are then described. They are promising candidates for on-body channels at 60 GHz. The first...
When the flip-chip packaging has been moving to the lead-free, fine-pitch and high-current-density packaging, the flip chip with copper-pillar-bump interconnects can provide a solution to this need. However, this package during the thermal cycling test (TCT) still suffers the reliability problems such as delamination at the Cu low-k materials or at the interface between the UBM (under bump metallurgy)...
Due to the increasing functional demand and miniaturization in high-density microelectronics packaging, thermomigration in flip chip solder joints owing to Joule heating becomes a serious reliability issue. In recent years, a series of researches have been devoted to examining the failure mechanism of thermomigration in eutectic SnPb and lead-free solder joints. However, only a few studies were focused...
Silicon-on-lattice engineered substrates (SOLES) are SOI substrates with embedded Ge layers that facilitate III-V compound integration for advanced integrated circuits. The new materials integration scheme in SOLES requires the analysis of its thermal stability and diffusion barrier properties. In this study, we report on the successful monolithic integration of CMOS/III-V transistors with a reduced...
MBE growth of InP-based HBTs on GeOI/Si substrates is described. A GaAs buffer is nucleated on the GeOI; then a graded InAlAs metamorphic buffer transitions the lattice constant to InP. TEM shows minimal anti-phase boundaries and limited dislocations propagating into the device layers. Large area DC parameters are similar to LM HBTs grown on InP. Small area devices exhibit peak current gain cutoff...
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